Research Talk


Georgios Giannakis

Georgios B. Giannakis (Fellow’97) received his Diploma in Electrical Engr. from the Ntl. Tech. Univ. of Athens, Greece, 1981. From 1982 to 1986 he was with the Univ. of Southern California (USC), where he received his MSc. in Electrical Engineering, 1983, MSc. in Mathematics, 1986, and Ph.D. in Electrical Engr., 1986. He was with the U. of Virginia from 1987 to 1998, and since 1999 he has been a professor with the U. of Minnesota, where he holds a Chair in Wireless Communications, a University of Minnesota McKnight Presidential Chair in ECE, and serves as director of the Digital Technology Center.  His general interests span the areas of communications, networking and statistical signal processing – subjects on which he has published more than 430 journal papers, 720 conference papers, 25 book chapters, two edited books and two research monographs (h-index 132). Current research focuses on data science and network science with applications to social, brain, and power networks with renewables. He is the (co-) inventor of 32 patents issued, and the (co-) recipient of 9 best journal paper awards from the IEEE Signal Processing (SP) and Communications Societies. He also received Technical Achievement Awards from the SP Society (2000), from EURASIP (2005), and the inaugural IEEE Fourier Tech. Field Award (2015). He is a Fellow of EURASIP, and has served the IEEE in various posts including that of a Distinguished Lecturer.

Title of The Talk: Sparsity and Low Rank for Inference of Cognitive Communication Network States

Abstract.: Viewed through a statistical inference lens, many challenges facing communication network analytics boil down to (non-) parametric regression and classification, dimensionality reduction, or clustering. Adopting such a vantage point, this keynote presentation will put forth novel learning approaches for comprehensive situation awareness of cognitive radio (CR) communication networks that include spatio-temporal sensing via RF spectrum and channel gain cartography, flagging of network anomalies, prediction of network processes, and dynamic topology inference. Key emphasis will be placed on parsimonious models leveraging sparsity, low-rank or low-dimensional manifolds, attributes that are instrumental for complexity reduction.

Sarah Harris

Sarah Harris is an Associate Professor at the University of Nevada, Las Vegas. She completed her B.S. at B.Y.U. and her M.S. and Ph.D. at Stanford University. She has worked at Hewlett Packard, Nvidia, and various other places. She worked at Harvey Mudd College as an assistant and then associate professor from 2004-2014 and joined UNLV in 2014. She also spent a year as a visiting professor at the Technische University of Darmstadt in Germany. Her research interests include embedded systems, biomedical engineering, and robotics. Outside of work, she enjoys playing music and spending with her kids.

Title of the Talk: Control algorithms for smooth prosthetic gait

Abstract: An estimated 23.6 million Americans are affected by Type II diabetes and 37,000 undergo lower limb amputation each year [CDC]. About half of these patients are prescribed a foot-ankle prosthesis, yet mobility is often severely restricted by pain and impaired walking dynamics — in turn, leading to cardiovascular disease and other comorbidities. In order to affect better health outcomes for persons with amputation, we have addressed the link between residual limb pathology and mechanical dysfunction of the prosthesis with what we call a Dynamic Intelligence System. This system allows the dynamics of a human wearer of prosthetics to enter the control loop of that prosthetic limb for the first time. This Dynamic Intelligence System mitigates the extreme environment at the prosthesis-residual limb interface by reducing the harsh impacts and oscillatory loads that cause compressive, shear, and bending stresses at the residual limb.

C.-C. Jay Kuo

Dr. C.-C. Jay Kuo received his Ph.D. degree from the Massachusetts Institute of Technology in 1987. He is now with the University of Southern California (USC) as Director of the Media Communications Laboratory and Distinguished Professor of Electrical Engineering and Computer Science. His research interests are in the areas of media processing, compression and understanding. Dr. Kuo was the Editor-in-Chief for the IEEE Trans. on Information Forensics and Security in 2012-2014. He was the Editor-in-Chief for the Journal of Visual Communication and Image Representation in 1997-2011, and served as Editor for 10 other international journals. Dr. Kuo received the 1992 National Science Foundation Young Investigator (NYI) Award, the 1993 National Science Foundation Presidential Faculty Fellow (PFF) Award, the 2010 Electronic Imaging Scientist of the Year Award, the 2010-11 Fulbright-Nokia Distinguished Chair in Information and Communications Technologies, the 2011 Pan Wen-Yuan Outstanding Research Award, the 2014 USC Northrop Grumman Excellence in Teaching Award, the 2016 USC Associates Award for Excellence in Teaching, the 2016 IEEE
Computer Society Taylor L. Booth Education Award, the 2016 IEEE Circuits and Systems Society John Choma Education Award, the 2016 IS&T Raymond C. Bowman Award, and the 2017 IEEE Leon K. Kirchmayer Graduate Teaching Award. Dr. Kuo is a Fellow of AAAS, IEEE and SPIE. He has guided 145 students to their Ph.D. degrees and supervised 27 postdoctoral research fellows. Dr. Kuo is a co-author of 260 journal papers, 900 conference papers and 14 books.

Title of the Talk: Interpretable Convolutional Neural Networks via Feedforward Design

Abstract:The superior performance of Convolutional Neural Networks (CNNs) has been demonstrated in
many applications such as image classification, detection and processing. Yet, CNN’s working principle remains a mystery. We offer an interpretable design for simple CNNs through a feedforward construction without backpropagation. A CNN is simple if it is a cascade of two networks; namely, the Conv net and the FC net. The Conv net consists of convolutional layers while the FC net contains fully connected layers. To design the Conv net, we develop a new signal transform, called the Saab (Subspace approximation with adjusted bias transform. The bias term in filter weights is chosen to annihilate nonlinearity of the activation function, which simplifies our design significantly. For the FC net design, we propose a label-guided linear least squared regression (L3SR) method. To shed light on the behavior of the FC net, we measure the cross-entropy at nodes of FC layers. The properties and performance of the traditional backpropagation design and the proposed feedforward design are compared and analyzed.

Jacques Christophe Rudell

Jacques “Chris”tophe Rudell received degrees in electrical engineering from the University of Michigan (BS), and UC Berkeley (MS, PhD). After completing his degrees, he worked for several years as an RF IC designer at Berkana Wireless (now Qualcomm), and Intel Corporation. In January 2009, he joined the faculty at the University of Washington, Seattle, where he is now an Associate Professor of Electrical and Computer Engineering. He is also a member of the Center for Neural Technology (CNT) and serves as the co-director of the Center for Design of Analog-Digital Integrated Circuits (CDADIC). While a PhD student at UC Berkeley, Dr. Rudell received the Demetri Angelakos Memorial Achievement Award, a citation given to one student per year by the EECS department. He has twice been co-recipient of best paper awards at the International Solid-State Circuits Conference, the first of which was the 1998 Jack Kilby Award, followed by the 2001 Lewis Winner Award. He received the 2008 ISSCC best evening session award, and best student paper awards at the 2011 and 2015 RFIC Symposium. Chris is recipient of the National Science Foundation (NSF) CAREER Award. Dr. Rudell served on the ISSCC technical program committee (2003-2010), and on the MTT-IMS Radio Frequency Integrated Circuits (RFIC) Symposium steering committee (2002- 2013), where he was the 2013 General Chair. He was an Associate Editor for the Journal of Solid-State Circuits (2009-2015).

Rudell received the National Science Foundation CAREER award for his work related to mmWave CMOS IC design. He has served on the IEEE International Solid-State Circuits Conference technical program committee (2003-2010), and on the RFIC steering committee (2002-2013) where he was the 2013 General Chair. He was also an Associate Editor for the IEEE Journal of Solid-State Circuits (2009-2015). Rudell is currently a member of the IEEE European Solid-State Circuit Conference’s technical program committee.

Title of the Talk: Memory Module Design, Architectures, and CommunicatioTwo Way Traffic Ahead: The Challenges and Future of Full Duplex Communications

Abstract: Integration of discrete radios onto a single-silicon CMOS substrate, followed by commercialization of single-chip cellular, Bluetooth, and Wi-Fi radios, has shaped the wireless world we live in today. Although integration of very large systems-on-chip (SoCs) which include wireless transceivers and powerful microprocessors, are commonplace in todays’ consumer electronics, the demand for lower power consumption, higher effective data rates, and higher network capacity continues to drive
research on integrated radios. By some estimates, the demand for mobile data per volume area will increase 1,000× during the next decade, with end-user data rates increasing by as much as 10–100×. A possible approach to close the gap between existing data rates and future demand could be the use of in-band full duplex communication which allows simultaneous communication using the same carrier frequency. However, realizing commercial single-chip radio solutions for full duplex communications presents numerous challenges. This presentation surveys the challenges and the current state-of-the-art in the areas of full duplex (FD) and frequency division duplex (FDD) integrated transceivers. Implementation hurdles in the form of the linearity, noise, bandwidth (BW) and power consumption of transmitter (TX) self- interference (SI) cancellation circuitry are explored. The difficulty of performing SI cancellation is heavily influenced by the modulation method, the maximum TX power output and the receiver (RX) channel BW. These issues are discussed using several recent publications as implementation examples of single-chip FD radios that range in performance from low-power cancellation techniques, to transceivers which target broad channel bandwidths using high-output-power Power Amplifiers, thus requiring deep SI cancellation.

Russel Jacob (Jake) Baker

Russel Jacob (Jake) Baker received the B.S. and M.S. degrees in electrical engineering from the University of Nevada, Las Vegas, in 1986 and 1988. He received the Ph.D. degree in electrical engineering from the University of Nevada, Reno in 1993.

From 1981 to 1987 he served in the United States Marine Corps Reserves (Fox Company, 2nd Battalion, 23rd Marines, 4th Marine Division). From 1985 to 1993 he worked for E. G. & G. Energy Measurements and the Lawrence Livermore National Laboratory designing nuclear diagnostic instrumentation for underground nuclear weapons tests at the Nevada test site. During this time he designed, and oversaw the fabrication and manufacture of, over 30 electronic and electro-optic instruments including high-speed cable and fiber-optic receiver/transmitters, PLLs, frame- and bit-syncs, data converters, streak-camera sweep circuits, Pockels cell drivers, micro-channel plate gating circuits, and analog oscilloscope electronics. In 1991-1992 he was an adjunct faculty member in the department of electrical engineering at the University of Nevada, Las Vegas (UNLV). From 1993 to 2000 he served on the faculty in the department of electrical engineering at the University of Idaho (UI). In 2000 he joined a new electrical and computer engineering program at Boise State University (BSU) where he served as department chair from 2004 to 2007. At BSU he helped establish graduate programs in electrical and computer engineering including, in 2006, the university’s second PhD degree. In 2012 he re-joined the faculty at UNLV. During his tenure at the UI, BSU, and UNLV he has been the major professor to more than 85 graduate students. In addition to this industry and academic experience, he has done technical and expert witness consulting for over 100 companies and laboratories.

Over the last 30+ years his research and development interests have been, or currently are, focused on analog and digital integrated circuit design and fabrication, design of diagnostic electrical and electro-optic instrumentation for scientific research, integrated electrical/biological circuits and systems, array (memory, imagers, and displays) fabrication and design, CAD tool development and online tutorials, low-power interconnect and packaging techniques, design of wired/wireless communication and interface circuits, circuit design for the use and storage of renewable energy, power electronics, and the delivery of online engineering education.

Professor Baker is the named inventor on 149 US patents. He is a member of the honor societies Eta Kappa Nu and Tau Beta Pi, a licensed Professional Engineer, a popular lecturer that has delivered over 50 invited talks around the world, an IEEE Fellow, and the author of the books CMOS Circuit Design, Layout, and Simulation, CMOS Mixed-Signal Circuit Design, and a coauthor of DRAM Circuit Design: Fundamental and High-Speed Topics. He received the 2000 Best Paper Award from the IEEE Power Electronics Society, the 2007 Frederick Emmons Terman Award, and the 2011 IEEE Circuits and Systems Education Award.

He currently serves, or has served, on the IEEE Press Editorial Board (1999-2004), as editor for the Wiley-IEEE Press Book Series on Microelectronic Systems (2010-2018), as the Technical Program Chair of the 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS 2015), as advisor for the student branch of the IEEE at UNLV (2013-present), on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee (2011-2016), as a Distinguished Lecturer for the SSCS (2012-2015), and as the Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for the IEEE Solid-State Circuits Magazine.

Title of the Talk: Memory Module Design, Architectures, and Communications

Abstract:This talk presents an overview of the main memory system and proposed future directions.
This includes a historic review of memory modules, current topologies and performance, and future directions including a proposed direction for future memory module design. Since sustaining performance gains has power consumption, capacity, and cost moving in the wrong direction with the current memory modules, a novel module and interconnect architectures is proposed. The proposed architectures utilize inexpensive innovations, including interconnect and packaging, to substantially reduce the power, and increase the capacity and bandwidth of the main memory system. A low cost advanced packaging technology is used to propose an 8
die and 32-die memory module. The 32-die memory module measures less than 2 cm3. The size and packaging technique allow the memory module to consume less power than conventional module designs. A 4 Gb DRAM architecture utilizing 64 data pins is proposed.
The DRAM architecture is inline with ITRS roadmaps and can consume 50% less power while increasing bandwidth by 100%. The large number of data pins are supported by a low power capacitive-coupled interconnect. The receivers developed for the capacitive interface were fabricated in 0.5 µm and 65 nm CMOS technologies as a proof of concept. The 0.5 µm design operated at 200 Mbps, used a coupling capacitor of 100 fF, and consumed less than 3 pJ/bit of energy. The 65 nm design operated at 4 Gbps, used a coupling capacitor of 15 fF, and consumed less than 15 fJ/bit.

Chuck Easttom

Chuck Easttom holds a Doctor of Science (D.Sc.) in Cyber Security as well as three master’s degrees (one in applied computer science and one in systems engineering). He is the author of 26 computer science books used as textbooks at over 60 universities. He has also authored dozens of scientific papers on a range of topics, and is an inventor with 15 computer science related patents. He is a member of the IEEE and ACM, and a Distinguished Speaker of the ACM. He is also a reviewer for several scientific journals including the IEEE Journal of Security and Privacy. He has worked on the IEEE Standards Committee in the 2675 DevOps Working Group. He is involved in research in a variety of areas including cryptography, cyber warfare, engineering processes, and digital forensics.

Title of the Talk: The impact of complexity and emergent properties on engineering

Abstract: Emergent properties in complex systems was first recognized in biological systems. In recent years various engineering disciplines, particularly systems engineering, have noted that emergent properties in complex systems can lead to unforeseen failures. However, there has been inadequate study of emergence in engineered system. This presentation will provide the essentials of emergence, specific impacts emergent properties have had on engineered systems, and suggestions for research to better understand and perhaps predict emergent properties in any engineered systems. The research spans multiple studies with the goal of providing some level of predictability to emergent properties in complex systems.

Important Deadlines

Full Paper Submission:30th November 2018
Acceptance Notification: 10th December 2018
Final Paper Submission:20th December 2018
Early Bird Registration: 20th December 2018
Presentation Submission: 31st December 2018
Conference: 7th-9th January 2019

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• Conference Proceedings will be submitted for publication at IEEE Xplore Digital Library
• Best Paper Award will be given for each tracks
• There will be two workshops on-
i. Data Analysis and ii. IoT on Jan 9, 2019
• There will be Corporate Exhibitions and Product Display on 7th and 8th January of 2019.
• Conference Record No-